1. Technical Field
This invention relates in general to electronic devices and, more particularly, to a method and apparatus for increasing the efficiency of a cache memory.
2. Description of the Related Art
Most modern day processing devices utilize a cache memory to increase processing speed. A cache memory acts as an intermediary between a processing circuit, such as a general purpose processor or a digital signal processor, and a memory bank, typically a dynamic random access memory (DRAM). The cache memory, typically a static random access memory (SRAM), is generally significantly smaller than the main memory bank (in terms of storage capacity), but significantly faster. The cache memory retains a portion of the data in the memory bank. When the processor accesses data, the cache memory is checked first to see if the data resides in the cache; if so, a "cache hit" ensues and data is taken from the cache memory which can supply the data at high speed responsive to the memory access request. On the other hand, if the data does not reside in the cache; if so, a "cache miss" ensues and data is taken from the memory bank. After a cache miss, the processor will generally be forced to wait for several clock cycles while the data is retrieved from the memory bank.
Cache architectures often have hit rates in the 90-95% rates, depending upon the application. The actual efficiency depends upon a number of factors, including the caching scheme employed, the size of the cache, and the application being run by the processor. Cache memories thus allow slower, less expensive, memory to store a large amount of data, while storing the portion of the data most likely to be accessed in the high speed cache memory.
While caches have significantly increased the speed at which data can be retrieved from the memory bank, cache architectures themselves can be slow relative to the capabilities of high speed processors. Further, a cache memory dissipates significant amounts of power, which is a particular concern to mobile electronic devices. Therefore, a need has arisen for a high speed, low power, cache architecture.